A Novel Five-Transistor SRAM Cell for High Speed and High Density Applications

A Novel Five-Transistor SRAM Cell for High Speed and High Density Applications

Abstract

To help overcome limits to the speed and density of conventional SRAMs, we have developed a five-transistor SRAM cell. The newly developed CMOS five-transistor SRAM uses one bit-line during read/write operation. This cell retains its data with leakage current and positive feedback without refresh cycle. The new cell size is 18% smaller than a conventional six-transistor cell using same design rules. Simulation results obtained from HSPICE 2008 in 0.25µm technology show new cell is 27% faster than conventional six-transistor cell. Furthermore, the analytical results are in good agreement with the improvement of speed in new cell.

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