A Systematic Method for Testing of Bus-Based Communication Structures of Complex Chips
Abstract
Bus based communication structures play a key role in communicating between components of high density chips such as System-on-Chip (SOC) and Network-on-Chip (NOC). Many static faults such as open circuit, short circuit, stuck-at and combination of them, and also such as crosstalk faults might occur in chip's bus-based communication structures during chip manufacture or in the normal operation of them. Former needs dedicated tests and the latter needs at-speed tests. In this paper we have exploited a systematic method to extract test patterns for both of static and crosstalk fault types, and proposed a very suitable solution for testing of chips’ buses through designing an at-speed test pattern generator for each of fault types with low area overhead.
Keywords
Communication Structures, Bus, Fault Model, Static Faults, Crosstalk
