Using Standard HDLs and CAD Tools for the Design and Simulation of Asynchronous Circuits
Abstract
In this paper we will show that it is both possible and easy to use a standard HDL language like Verilog HDL, along with PLI to model asynchronous circuits at all levels of abstraction, including the behavioral level (CSP level). Our method allows CSP (Communicating Sequential Processes) codes to be simulated on ordinary Verilog simulators. The suggested algorithm is easy to implement (less than 100 lines of code in our case), thus other asynchronous designers not only can implement their own codes, but also they can further improve and optimize the method. In this way, one can customize the way that CSP features are added to Verilog HDL. Furthermore, it does not need any preprocessing or extra tool. The designer can write his code in Verilog language from the very beginning steps of the design, while channel communications become like atomic actions, and fine-grained concurrency within processes is available.
We believe that this method has the potential to override methods that involve CSP-like languages and new simulators for asynchronous circuits which are described by CSP-like languages, and enables designers to exchange their codes easily.
Keywords
asynchronous circuits, Verilog, modeling
