A Non-interference Isolation Mapping to Eliminate Timing Channel Attacks
Abstract
On-chip network security is a dominant necessity for secure many-core platforms to leverage the concepts of the cloud and embedded system-on-chip. In fact, there is a need for a secure, low-latency and highly utilized on-chip communication. While there are various techniques to mitigate and eliminate timing side-channel attacks, these attacks present a security threat for networks-on-chip (NoCs). This threat stems from the experienced latencies of the malicious application, which can divulge information when the victim applications are accessing shared resources. We propose an approach to eliminate the timing side-channel attacks, using isolation dynamic mapping. In order to meet the non-interference flows between malicious and victim applications and the security of the NoC, our proposed schemes (Isolated and Liso) employ several techniques, including (1) a scalable strategy that maximizes utilization of the system, and (2) a low-overhead isolation approach for the NoC through rectangular and L-shape mappings. We show that Isolated mapping scheme degrades the throughput of our secure NoC system while Liso scheme improves it without leaking information. Our best solution offers throughput that is on average 16\% lower than that of an optimized non-secure baseline, and has no router modification in contrast to the best known competing schemes.
Keywords
Non-interference, Security, On-Chip Networks, Timing Side-Channel Attacks
