Novel Designs of Fast Parity-Preserving Reversible Vedic Multiplier

Novel Designs of Fast Parity-Preserving Reversible Vedic Multiplier

Abstract

Reversible logic is a new technology that is considered as an essential requirement for the design of quantum computers. In the calculation unit of computers, multiplication is one of the most frequently used operations. In this paper, we propose new optimized algorithms to design a parity-preserving reversible Vedic multiplier. Three approaches for designing optimized reversible Vedic multiplier circuits are proposed which are better than the existing circuits in terms of quantum cost, number of garbage outputs, number of constant inputs, and other criteria. The proposed reversible Vedic multipliers can be generalized to produce parity-preserving n*n reversible multiplier. We have also achieved some relations which can calculate the quantum cost, the number of constant inputs, and the number of required garbage outputs for the proposed Vedic circuit of any dimension. We have shown that our proposed reversible Vedic multiplier in n*n scale is the best compared to the existing Vedic multipliers.

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