A Reconfigurable, Pipeline Decimal Multiplier

A Reconfigurable, Pipeline Decimal Multiplier

Abstract

After addition, multiplication is one of the most frequently used arithmetic operations. As such, numerous combinational or sequential multipliers have been introduced during the last few decades. Most of these multipliers are binary and only a small portion is decimal. However, decimal arithmetic in general and decimal multiplication in particular is gaining prominence. On the other hand, the ever-changing requirements of various applications have imposed a significant demand for reconfigurable designs. In this paper, a reconfigurable 16-digit by 16-digit decimal multiplier is proposed. Since the design is done hierarchically, a building block of a 4-digit by 4-digit combinational multiplier is proposed based on a discussion on the appropriate granularity of the building block. It will be shown that using 4221 coding (instead of BCD) and CSA adders in these blocks will lead to minimum delay. The optimized 4-digit multiplier blocks are devised in a pipeline structure that is inspired by lattice multipliers. For a given maximum latency, Pareto optimal points for a 16-digit by 16-digit decimal multiplier will be obtained. The proposed architecture is reconfigurable in terms of multiplicand and multiplier width. Synthesis results show that the reconfigurebility overhead in terms of area and delay is negligible.

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