Process-Variation-Aware Instruction Rescheduling to Reduce Leakage in Nanometer Instruction Caches

Process-Variation-Aware Instruction Rescheduling to Reduce Leakage in Nanometer Instruction Caches

Abstract

Process variation, despite introducing challenges in stability and power of SRAM memories, provides a new opportunity for leakage-power reduction: statistical simulation shows that the same SRAM cell leaks differently when storing 0 and 1; this difference is as high as 57% at 60mv variation of threshold voltage (Vth). Thus, leakage can be reduced if values with less leakage can be stored in the cells. We show applicability of this proposal by presenting a first technique for reducing instruction cache leakage: we reorder instructions within basic-blocks so as to match up the instructions with the less-leaky state of their corresponding cache cells. Experimental results show up to 12.51%, averaging 10.73%, leakage energy reduction at 60mv variation in Vth, and that this saving increases with technology scaling. Since intra-basic-block rescheduling does not affect instruction cache hit ratio, this reduction is provided with only a negligible penalty, in rare cases, in the data cache.

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