A Specification-Driven Framework for the Floorplanning and Placement of Hierarchical VLSI Designs

A Specification-Driven Framework for the Floorplanning and Placement of Hierarchical VLSI Designs

Abstract

With the growing complexity of VLSI systems, automatic physical design of today's systems has become very complex. One approach to control overall complexity is to divide the design into several levels of hierarchy. This may produce poor results if the inter-dependence between various components of the design is not considered, In addition, the high degree of inter-dependence between design processes operating at the physical and higher levels of abstraction (e.g. the specification level) necessitates a number of iterations between these levels. One solution, exploited by this work, is the use of a common design hierarchy far both specification and physical level design. This can provide physical data to the specification level synthesis process, thereby reducing the design cycle. In this paper, a framework for the floorplanning and placement of macrocell designs is introduced. Inter-dependence between levels of a design specification hierarchy is taken into account in this framework. Since the framework is not inherently restricted by either the hierarchy depth or the hierarchy branching factor, it is able to preserve an arbitrary specification hierarchy. The framework gathers geometric information about the design over several traversals of the design specification hierarchy and sets the physical geometries, such as port positions, orientation, etc., in a stepwise refinement fashion. The results show that the framework produces good results quickly for large designs.

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