Search All Articles

Search by:
FinFET Based Level Converter for Multi-VDD System Design
Majid Moghaddam • Mohammad Hossein Moaiyeri • Mohammad Eshghi
Keywords: Multi-Vt • Low-Power Design • Single-Supply Level Converter • Independent Gate FinFET • Multi-VDD
A Low-Power Hierarchical FinFET-Based SRAM
Somayeh Maabi • Sina Sayyah Ensan • Mohammad Hossein Moaiyeri • Shaahin Hessabi
Keywords: Static Random Access Memory (SRAM) • Multiport Memories • Low-Power Design • Static Noise Margin (SNM) • FinFET • Nanoelectronics
Architecture-Level Design Space Exploration for Radix-16 Sequential Multipliers
Saba Amanollahi • Ghassem Jaberipur
Keywords: Sequential Multiplier • Design Space Exploration • Adder Architectures • Energy Efficiency
A New Tri-State Based Static Random Access Memory with Improved Write-Ability and Read Stability
Ghasem Pasandi • Sied Mehdi Fakhraie • Ehsan Qasemi
Keywords: Bulk CMOS • Fin FET • Low Power Design • Memory • Sub Threshold • Sense Amplifier • Static Random Access • Memory (SRAM)
A Generic Modulo 2^n –1 Adder Based on Stored Negabit Representation of Residues
Ghassem Jaberipur
Keywords: Generic Arithmetic Components • Low Power Design • Modulo 2^n–1 Addition • Residue Arithmetic
Process-Variation-Aware Instruction Rescheduling to Reduce Leakage in Nanometer Instruction Caches
Maziar Goudarzi • Tohru Ishihara
Keywords: Process Variation • Leakage Power • Instruction Cache • Instruction Rescheduling • Low-Power Design
Evolutionary Relational Database Schema Design Based on Software Measurement
Amin Rouzbahani • Seyed-Hassan Mirian-Hosseinabadi
Keywords: Relational Database Design • Quality Evaluation • Software Measurement • Genetic Algorithms
A Similarity-Based Framework for Integrated Temporal Partitioning and Physical Design of Reconfigurable Computing Systems
Farhad Mehdipour • Morteza Saheb Zamani • Hamid Reza Ahmadifar • Mehdi Sedighi
Keywords: reconfigurable computing systems • design flow • temporal partitioning • physical design • placement • routing • dummy node
Design and Analysis of a Fully-Distributed Parallel Packet Switch with Buffered Demultiplexers
Ali Asghar Khodaparast • Siavash Khorsandi
Keywords: system design • parallel packet switch • load balancing • synchronization • multistage switch
A Specification-Driven Framework for the Floorplanning and Placement of Hierarchical VLSI Designs
Morteza Saheb Zamani
Keywords: VLSI • physical design • floorplanning • placement • specification hierarchy
Pages: 1 2 »
About Journal
Editorial Board
Guide For Authors
Submit Your Manuscript
Latest Issue
Past Issues
© Copyright - The CSI Journal on Computer Science and Engineering
Produced by Intelligent Information Solutions Center